The present invention relates to memory systems with redundant memory cells. More particularly, the present invention relates to the replacement of rows or columns in dual port memory systems using a reduced number of replacement fuses.
Advances in semiconductor fabrication techniques and in memory design have led to the commercial production of semiconductor memories which hold millions of bits of information. It is important that a manufacturer verify that each and every bit on chip are addressable before the chip is sold. However, due to the large number of bits on each chip, it is unrealistic to assume that chips can be fabricated with every bit position functioning. Physical defects in the manufacturing process tend to make it very difficult to manufacture devices of such a high bit density without one or more bits becoming defective. A manufacturer cannot sell a memory chip without ensuring that the full range of addresses are functional. Discarding chips having defective bits is wasteful, inefficient and costly. Thus, it is desirable to provide an approach which allows fabrication of a memory chip with redundant bits to compensate for the inevitable bit defects.
Designers have incorporated one or more redundant rows or columns into memory devices to provide a method of patching bit errors in memory chips. That is, redundant cells are provided which can be accessed when testing indicates the existence of bit defects in the memory. If, for example, a bit in a first column of a memory array is found to be defective, the entire first column is typically replaced by a substitute column. The patch is accomplished using a bank of polysilicon fuses. The address of the patched column is burned into the fuse bank using techniques known in the art. Thus, whenever the address of the defective column is presented to the memory, the replacement column will be accessed instead. This solution reduces the number of memory chips which are unusable due to defective bits. The solution, however, is costly in terms of the die space consumed by the fuse banks and the attendant comparator logic.
As a simple illustrative example, a single array of memory elements is formed from a number of physical rows and columns. The intersection of the rows and columns are bits which can be individually addressed. If one of these bits is defective, e.g., as a result of manufacturing or process defects, it must be replaced. It is generally considered impractical to repair bits within one physically continuous row or column without repairing all others in that row or column. Thus, if a bit is defective in, e.g., column A0, the entire column A0 may be replaced. A typical fuse bank which may be used to replace an entire row or column of a memory array could include two fuses for each address line (e.g., for line A0 and its compliment). Thus, using this approach, eighteen fuses would be needed to replace a single column or row for a nine bit wide address. The fuse bank is "programmed" by blowing appropriate fuses to indicate the address of the column or row to be replaced. These fuses are typically blown using a laser beam to burn open conductive polysilicon links. The code from the fuse bank is then sent to an address comparator. If the address sent to the memory array matches that stored in the fuse bank, the column normally accessed by that address is not accessed. The replacement column is accessed instead. This redundancy technique is particularly wasteful when the number of bits within a column becomes large, since a large number of bits are being committed for repair when only a relatively few are actually defective. The technique not only wastes bits, it also consumes a substantial amount of valuable die space. In this simple example, for a nine bit wide address, a total of eighteen fuses and a minimum of twenty-one transistors are needed (in addition to any transistors needed in an address comparator circuit) to implement a single replacement column.
The amount of die area consumed by fuses and compare logic can cause the die size of a memory device to grow with the number of total possible repairs. The fuses themselves consume die space. Valuable substrate area is further eroded as each fuse must be surrounded by a blank or "field" area to allow a laser beam to blow the fuse reliably without damaging nearby circuitry. Even with modern laser repair equipment, the fuse "pitch", i.e., the distance from the center of one fuse to the center of the next fuse, is typically four to six microns and the height of the fuse is typically six to eight microns. The die area associated with the fuse banks and compare blocks in such a scheme can approach several percent of the total die. Additional manufacturing cost is encountered from the physical blowing of all of the fuses. Thus, it is desirable to provide a redundancy approach which uses fewer fuses and which wastes fewer functional bits.
One way to reduce the number of wasted functional bits in, e.g., a repaired column, is to divide the memory into multiple physical arrays. Each sub-array can be repaired independently of the other sub-arrays, using local redundant rows and columns lying adjacent to each sub-array. This redundancy technique is more efficient than the single array scheme for a given number of redundant bits of storage, since fewer bits must be committed to repair for each row or column replacement and therefore more independent repairs are possible.
While the divided array allows more independent repairs for a given amount of redundant storage, the larger number of repairs is necessarily associated with a larger number of fuse banks. Essentially, each sub-array must have associated with it one fuse bank for each redundant row or column address repaired within that array. For example, if there are two redundant rows and two redundant columns within each sub-array, a memory device containing 16 sub arrays will contain 16.times.2.times.2=64 fuse banks, each with its own address comparator logic. The amount of die area consumed by these fuses and compare logic can cause the die size to grow substantially with the number of total possible repairs.
To reduce the number of fuses required to program a repaired address, designers have resorted to predecoded address schemes. Such predecoded schemes can reduce the number of fuses required to as low as log.sub.2 n+1 (where n is the number of address lines), although such schemes generally trade off a smaller number of fuses for considerably more transistors and interconnect in the address compare logic. Often, the predecoded addresses already exist to perform other functions; however, additional logic gates are required to implement the predecoded redundant address scheme. Whether the decoded or the non-decoded redundant address scheme consumes less die area is a function of lithographic design rules and the limitations of the laser repair equipment used and could differ for each application.
While the predecoding approach to redundant columns is helpful in reducing the number of fuses in typical systems, there are certain applications for which it is not particularly well suited. For example, the problem of redundancy and repair is complicated in multi-ported memory devices, such as the generalized dual port memory 10 shown in FIG. 1, or the devices disclosed in U.S. Pat. Nos. 4,636,986, 4,648,077, 4,747,081, or 4,866,678. These devices typically contain a random access memory (RAM) port 16 and a serial access memory (SAM) port 18. The SAM 14 may be, e.g., a serial register configured to receive a single addressed row from the RAM 12. Once the row of memory is transferred to the SAM, the SAM can be serially accessed independently and asynchronously to the RAM operation. One or more redundant columns 24 must be included for repair of bits in the RAM portion of memory. Correspondingly, one or more SAM register cells must also be replaced with redundant register cells 26 and programmed such that the redundant SAM register is accessed whenever it is desired to access data which has been transferred into the SAM from a corresponding redundant column in array 12. Typically, the SAM is accessed serially by fashioning the SAM as a small random access memory (RAM) and including a presettable counter used to provide addresses in sequence to the SAM. These addresses bear a one to one correspondence with the column addresses assigned to the memory array 12. Due to the asynchronous nature of the two ports after the transfer has occurred, the RAM 12 will typically access the repaired column address at a different time than when the SAM 14 will access the corresponding repaired SAM address via the counter and SAM control circuitry 22. Consequently, separate fuses and compare logic have traditionally been used on dual port memories for the columns of the RAM and the register cells of the SAM. The number of fuses is doubled even when a predecoding approach is used for the redundant RAM column addresses, due to the current need for separate fuses for the SAM. As discussed, this doubling of the repair circuitry is undesirable as it consumes valuable die area.
Accordingly, what is needed is an approach which provides redundant storage locations in dual port memory systems in a manner minimizing the amount of die area consumed by fuses and replacement circuitry. Preferably, the approach will eliminate the need to use separate fuse circuitry for the two ports of the memory.